1. Field of the Invention
One disclosed aspect of the embodiments relates to a solid-state imaging device used in a scanner, a video camera, or a digital still camera.
2. Description of the Related Art
Recently, a complementary metal oxide semiconductor (CMOS) image sensor has been widely used in a digital camera, a digital video camera, or a camera unit in a cellular phone. Further, a CMOS image sensor which includes an analog-digital (AD) conversion circuit is in development in response to a demand to reduce the number of components and power consumption. An example of such a CMOS image sensor employs a column AD conversion circuit (ADC) technique in which an ADC is arranged in each column of a pixel array. A column ADC based on ramp architecture is a well-known type of the A/D conversion method used in the column ADC.
The column ADC based on ramp architecture includes a comparator and a ramp signal source arranged in each column. The comparator compares a ramp signal, i.e., a reference signal, with a pixel signal, and measures the time required for a magnitude relation between a potential of the pixel signal and a potential of the ramp signal to be inverted. The comparator then stores the measured time as digital data in a column memory arranged in each column. For example, Japanese Patent Application Laid-Open No. 2009-60327 discusses a method which uses one counter, i.e., a common counter, that counts the reference signal (i.e., a slope signal) and the time from when a voltage of the reference signal starts to change from an initial voltage.
Japanese Patent Application Laid-Open No. 2009-60327 discusses a solid-state imaging device employing the column ADC based on ramp architecture. In the solid-state imaging device, the counter starts counting, with respect to the voltage of when the pixel has been reset, from the time the reference signal has started to change to the time when a comparison result signal has become inverted. The solid-state imaging device then stores in a storing unit (i.e., the N memory) a count value which the counter has counted. The counter then starts counting, for a signal reading voltage of when the pixel has not been reset, from the time the reference signal has started to change to the time when a comparison result signal has become inverted. The solid-state imaging device then stores in a storing unit (i.e., the S memory) a count value which the counter has counted.
A subsequent circuit performs digital correlated double sampling (CDS) processing in which a difference between the count values in the N memory and the S memory is acquired, and a signal component of the pixel is extracted. A count pulse (i.e., the count value) supplied from the counter is then sequentially propagated to the storing unit from the side closer to the counter. In such a method, if propagation delay of the count pulse supplied from the counter to the N memory in a column is different from the propagation delay of the count pulse supplied from the counter to the S memory in the same column, the following problem occurs.
For example, if images are captured in a dark state, the voltage when the pixel is reset is the same as the signal readout voltage when the pixel is not reset. The count values stored in the N memory and the S memory thus become the same. As a result, the signal component of the pixel extracted by the digital CDS processing becomes 0.
However, the propagation delay of the count pulse supplied from the counter to the N memory in a column may be different from the propagation delay of the count pulse supplied from the counter to the S memory in the same column. In such a case, the count values stored in the N memory and the S memory do not become the same, and the extracted signal component includes an offset, and does not become 0. The offset becomes a fixed noise component in each column and thus causes image deterioration.